1. Field of the Invention
The present invention relates to a detecting amplifier included in a reading section in which data are read out of a data storage section disposed in an integrated circuit.
2. Description of the Related Art
In an integrated circuit in which a logic circuit section and a memory circuit section are disposed within the same chip, the memory circuit section has an input section, a decoding section, a selecting section, a detecting amplifier, and an output section. The input section receives address data for designating a memory transistor for reading stored data out of a memory array section. The decoding section makes X and Y directional data for specifying the memory transistor based on the address data. The selecting section selects the stored data read out of the memory array section on the basis of an output signal of the decoding section. The detecting amplifier detects an electric potential of data transmitted from the selecting section. The output section transmits data from the detecting amplifier to a constructional portion outside the memory circuit section.
The memory array section has a well-known circuit structure. The selecting section has a well-known circuit structure. The memory array section and the selecting section constitute a semiconductor memory means.
The above detecting amplifier comprises two N-channel MOS transistors, two P-channel MOS transistors and two inverters, and further comprises two N-channel MOS transistors for negative feedback of the inverters.
An input side of the detecting amplifier connected to the selecting section is connected to source sides of the two N-channel MOS transistors and an input side of a first inverter. An N-channel MOS transistor is called an NMOS transistor in the following description. An output side of the first inverter is connected to gates of the two NMOS transistors. A drain side of one NMOS transistor is connected in series to a drain side of a P-channel MOS transistor. The P-channel MOS transistor is called a PMOS transistor in the following description. An electric signal .phi. p described later is supplied to a gate of the PMOS transistor. A source side of the PMOS transistor is connected to a positive power source. A drain side of another NMOS transistor is connected in series to a drain side of another PMOS transistor. A gate of another PMOS transistor is connected to the ground. A source side of another PMOS transistor is connected to a positive power source.
Two NMOS transistors for negative feedback are connected in series to each other between an output side of the first inverter and the input side of the detecting amplifier. These two NMOS transistors for negative feedback are disposed to remove noises in a positive direction caused in the detecting amplifier. A gate of one NMOS transistor for negative feedback is connected to a connection point between another PMOS transistor and another NMOS transistor. The above electric signal .phi. p is supplied to a gate of another NMOS transistor for negative feedback. The connection point between another PMOS transistor and another NMOS transistor is connected to an input side of the above output section through a second inverter.
An operation of the detecting amplifier constructed as above will next be explained. Data transmitted from the selecting section are first supplied to the first inverter so that a signal potential level is inverted by this first inverter. This inverted signal is then supplied to the gate of another NMOS transistor to control turning-on and turning-off operations of another NMOS transistor. Namely, the first inverter is operated to approximately maintain an input side potential of the detecting amplifier at the inverted potential level of the first inverter.
For example, when a memory transistor selected within the memory array section has a high resistance or is turned off, the input side potential of the detecting amplifier is set to a high potential. Accordingly, the potential level of an electric signal supplied to the gate of another NMOS transistor is changed by an action of the first inverter so that another NMOS transistor is turned off. Therefore, an input side of the second inverter disposed in the output section of the detecting amplifier is connected to the positive power source through another PMOS transistor turned on at any time. Accordingly, the input side of the second inverter has a high potential level so that a potential level of the detecting amplifier on an output side thereof is changed to a low potential level by the action of the second inverter.
In contrast to this, when the above memory transistor selected within the memory array section has a low resistance or is turned on, another NMOS transistor is turned on by the action of the first inverter and this turning-on state is held. The input side of the second inverter has a relatively low potential level determined by an electric current flowing through another PMOS transistor and a turning-on electric current of the above memory transistor. In this case, the above potential cannot be held on the input side of the detecting amplifier by a turning-on resistance value of another PMOS transistor. Accordingly, there is a case in which the input side of the detecting amplifier has a potential lower than the inverted potential of the first inverter.
Thereafter, when the next selected memory transistor has a high resistance or is turned off, no detecting amplifier is normally operated until the input side potential of the detecting amplifier is recovered. Namely, another NMOS transistor is not turned off. A time required to recover the input side potential of the detecting amplifier is determined by the turning-on resistance value of another PMOS transistor. Normally, this turning-on resistance value of another PMOS transistor is set to a considerably large value so as to provide a sufficiently large potential difference by a turning-on electric current of the memory transistor which does not have a large current value. Accordingly, it takes much time to recover the input side potential of the detecting amplifier.
The PMOS transistor and the NMOS transistor are disposed to solve this problem. An operation of the PMOS transistor is controlled by inputting a clock signal to the gate of this PMOS transistor. The NMOS transistor is connected in series to the PMOS transistor. The output voltage of the first inverter is applied to a gate of the NMOS transistor. Turning-on resistance values of the PMOS transistor and the NMOS transistor are set to be relatively low so as to rapidly recover the input side potential of the detecting amplifier.
However, in the above detecting amplifier, no input side of the second inverter for output can have a normal electric potential for a period providing a low potential level of the clock signal since a turning-on electric current of a memory transistor and electric currents of the PMOS transistor and the NMOS transistor are detoured on the input side of the second inverter. Therefore, no detecting amplifier is normally operated. This problem constitutes a first problem. Accordingly, no access time can be set to be shorter than a constant time irrespective a solving method for reducing the above long recovery time.
Further, there is a possibility that no sufficiently low potential can be supplied to the second inverter by dispersions in turning-on resistance value of another PMOS transistor and turning-on electric current of the memory transistor. This problem constitutes a second problem.
In the general detecting amplifier, when the memory transistor has a high resistance or is turned off and the clock signal has a high potential level, input and output sides of the first inverter are short-circuited. Accordingly, the input side of the detecting amplifier temporarily has a low resistance value to absorb noises and maintain the inverted potential of the first inverter. In this case, no detecting amplifier can be normally operated. This problem constitutes a third problem. Furthermore, it takes much time to recover this inverted potential so that no access time can be set to be shorter than a constant time.